On June 18, 2026, No Priors released a long-form interview with Intel CEO Lip-Bu Tan, titled Re-engineering the Semiconductor Supply Chain with Intel CEO Lip-Bu Tan.
Tan is not just speaking as the current CEO of Intel.
He founded Walden International in 1987 and has spent nearly four decades investing across semiconductors, AI, and advanced computing. He also served as CEO of Cadence from 2009 to 2021. In Intel’s announcement of his appointment, the company noted that during his tenure at Cadence, revenue more than doubled, operating margin expanded, and the stock rose more than 3,200%.
In March 2025, Tan was appointed CEO of Intel. Intel’s stock rose 14% the day after the announcement. Based on historical closing prices provided in our data set, Intel shares rose from $25.92 on March 18, 2025, the day Tan officially took over, to $140.94 on June 22, 2026 — a gain of roughly 444%.
That price move is not the focus of this article. It does, however, explain why the market pays attention when Tan discusses the semiconductor supply chain.
The more important part of the interview is not Intel’s stock chart. It is Tan’s broader industry framework: AI semiconductor demand is moving beyond single-chip performance and into a wider set of system constraints — memory, interconnect, power delivery, advanced packaging, new materials, AI-native EDA, and the migration of compute from data centers toward PCs, edge devices, and physical AI.
This article breaks down that framework from an industry and business-model perspective.
1. Tan’s Core Point: AI Semiconductors Should Not Be Analyzed One Chip at a Time
Tan’s discussion is not centered on one chip, one process node, or one company. His broader point is that as AI workloads scale, the pressure moves across the entire semiconductor system.
The first-principles logic is straightforward.
An AI model does not run on a chip in isolation. Training and inference require compute, memory, data movement, power delivery, thermal management, packaging, software scheduling, and system-level coordination. If any one of those layers becomes constrained, the performance of the whole system is affected.
Accelerators perform the compute. But the compute units need to be fed with data. That data comes from memory, which needs enough capacity and bandwidth. Once multiple accelerators are connected into a cluster, chips, servers, and racks need high-speed interconnect. As power rises, the challenge is not only whether a data center can access enough electricity, but also how efficiently power can be delivered near the processor. As chips get larger and more complex, advanced packaging determines whether CPUs, GPUs, HBM, I/O dies, and chiplets can become one manufacturable system. As traditional material paths run into physical limits, materials such as InP, GaN, SiC, glass substrates, and synthetic diamond enter the discussion. As chip complexity rises, EDA and simulation tools also become bottlenecks.
That is the important takeaway from Tan’s framework: AI semiconductors are not a single-point demand story. They are a system-constraint story.
A system constraint is not an abstract phrase. It means that a component or process that used to look like a supporting part can become a limiting factor for customer delivery, unit economics, power efficiency, deployment density, and product roadmaps.
Once customers start paying to solve that constraint, value begins to move across the supply chain.
So the better question is not simply: who makes AI chips?
The better questions are:
Which part of the system is limiting AI scale? Is the constraint cyclical or structural? Are customers already paying to solve it through long-term supply agreements, acquisitions, architecture changes, or higher component value? Is the business model a cyclical commodity, a core material, a system interface, or a long-duration design tool?
That is the real value of the interview.
2. Memory and HBM: The Most Visible Bottleneck Has Already Become Strategic
Among all the bottlenecks Tan discusses, memory is the easiest to verify.
The logic is simple: compute is only useful if data can reach the compute units fast enough. If memory bandwidth is insufficient, even the most powerful accelerator will sit idle. Training requires rapid access to model parameters. Inference requires context handling, KV cache, batching, and repeated interaction. The larger the model, the longer the context, and the higher the concurrency, the more important memory bandwidth and capacity become.
That is why HBM has been reclassified by the market.
DRAM has historically been treated as a cyclical commodity. When prices rise, profits surge. When supply catches up, pricing falls and the cycle turns. HBM is different. It is packaged directly with AI accelerators and affects system performance, energy efficiency, and supply reliability.
For AI customers, memory is no longer just a replaceable component. It is part of the system architecture.
Micron’s fiscal Q2 2026 results framed the company’s performance and outlook around the “strategic value of memory in the AI era.” That phrasing matters because it signals a shift in how memory is being positioned: from commodity input to infrastructure-critical resource.
SK Hynix provides an even clearer industry example. In June 2026, Reuters reported that SK Hynix had overtaken Samsung Electronics to become South Korea’s most valuable listed company, driven by its leadership in HBM. The same report cited estimated 2025 HBM market share of roughly 61% for SK Hynix, 21% for Micron, and 17% for Samsung.
The memory bottleneck is no longer theoretical. It is visible in supply-demand dynamics, earnings language, and market valuation.
But because memory has become so visible, the information gap is smaller.
The next layer of analysis is no longer “Is HBM important?” That question has already been answered. The more useful questions are:
Can long-term customer agreements change the cyclicality of the memory business? Will HBM supply remain tight after the next wave of capacity expansion? Can Samsung narrow the gap and change industry pricing power? Will inference architecture change the memory hierarchy through CXL, tiered memory, KV-cache offloading, local memory, or cloud-side caching? Will advanced packaging capacity become a secondary constraint for memory vendors?
The conclusion is not that memory companies will benefit indefinitely. The conclusion is more precise: HBM proves that AI semiconductor value is moving from pure compute expansion toward system-resource constraints.
3. Interconnect and Optical: Data Movement Is Becoming a System Cost
Tan also discusses high-speed interconnect and optical-related examples. The common issue behind them is the rising cost of data movement inside AI clusters.
A faster GPU does not automatically mean a faster cluster.
As AI infrastructure scales from single nodes to racks, and from racks to large clusters, the bottleneck shifts toward moving data efficiently. GPUs need to communicate with GPUs. GPUs need to communicate with memory. Servers need to communicate with other servers. Racks need to communicate with other racks.
All of this requires higher bandwidth, lower latency, and lower power per bit.
Historically, interconnect was often treated as a supporting layer. In AI clusters, it increasingly affects training efficiency, inference cost, energy consumption, and total cost of ownership.
Credo provides one commercial signal. The company reported fiscal Q4 2026 revenue of $437 million, up 157% year over year. The point is not to treat that as an investment conclusion. The point is that high-speed, low-power connectivity has moved from technical narrative into actual customer demand.
Marvell’s acquisition of Celestial AI provides another signal. Celestial AI is working on photonic fabric for next-generation data center scale-up connectivity. In its acquisition announcement, Marvell said Celestial AI is expected to begin contributing revenue in the second half of fiscal 2028, reach a $500 million annualized run rate by Q4 fiscal 2028, and reach a $1 billion annualized run rate by Q4 fiscal 2029.
That tells us optical interconnect and photonic fabric are no longer just lab-stage concepts. They are entering the roadmaps and revenue models of major semiconductor companies.
The industry point is not “optical is exciting.” The industry point is that as AI clusters scale, the connection architecture itself becomes a performance constraint.
Electrical connections face limits in power, distance, and density. Larger clusters make the energy and latency cost of data movement harder to ignore. Optical interconnect becomes commercially relevant when it can reduce the power and latency burden of moving data at scale.
That does not mean every optical component, optical module, or materials supplier benefits equally.
This layer needs to be separated into three groups:
First, high-speed connectivity solutions already used in AI data infrastructure. Second, optical interconnect technologies still going through product validation and architecture adoption. Third, upstream optoelectronic materials and devices that may matter over a longer time horizon.
They all relate to data movement, but their commercial maturity is very different.
VIUS’s view is that interconnect and optical are becoming more important because they address system efficiency at AI-cluster scale. The question is not whether a company is associated with optical technology. The question is whether customers are already paying for lower-power, higher-bandwidth, lower-latency data movement.
4. Power Delivery: The AI Power Problem Is Moving Inside the Server
The fact that AI data centers need more power is already well understood. Tan’s discussion of Empower and IVR moves the question deeper into the semiconductor system.
There are at least three layers to the AI power problem.
The first is whether the data center can access enough electricity. The second is whether the rack can handle higher power density and cooling. The third is whether power can be delivered near the compute unit with shorter paths, lower losses, and higher efficiency.
The third layer is where power delivery becomes a semiconductor issue.
As AI accelerators consume more power, conversion losses become heat. Heat limits deployment density and system stability. If power delivery cannot keep up, peak chip performance cannot be sustained, and server design becomes constrained.
ADI’s acquisition of Empower Semiconductor is a strong commercial signal. In May 2026, ADI announced it would acquire Empower for $1.5 billion in cash. In the announcement, ADI stated that as AI compute expands, the limiting factor is no longer only total watts, but power density. Supplying high-density, high-efficiency power close to the compute engine has become a key system-design challenge.
That is a very specific statement.
It means power delivery is no longer just a conventional analog or power-management function. It is becoming part of the AI compute-density problem.
This is where the industry analysis needs to be careful. “AI power” should not be reduced to the grid, transformers, gas turbines, or liquid cooling. Those are important infrastructure layers, but Tan’s reference to IVR and Empower points to power conversion inside the semiconductor system.
The business model is also different.
This is not simply about supplying more generic power chips. The key question is whether a product can enter the critical power path of an AI server, whether efficiency, footprint, thermal behavior, and reliability can win design slots, and whether the solution becomes part of the customer’s next-generation platform.
VIUS’s view is that power delivery is a micro-bottleneck that is easy to miss if the discussion stays at the macro power level. The commercial validation has already begun through M&A. The next layer of analysis is product position, customer adoption, and revenue contribution — not a broad claim that every power semiconductor company benefits from AI.
5. Advanced Packaging and Substrates: The Second Performance Curve After Process Scaling
Process technology still matters. But it is no longer the only path to performance.
As transistor scaling becomes more expensive, system performance increasingly depends on how multiple chips are combined. CPUs, GPUs, HBM, I/O dies, and chiplets need to become one high-bandwidth, low-latency, thermally manageable, manufacturable system.
That is why advanced packaging is moving from a back-end process to a core part of system performance.
TSMC’s CoWoS is the clearest industry example. AI accelerators depend on advanced packaging to connect GPUs and HBM at high bandwidth. CoWoS capacity has at times influenced the delivery pace of AI accelerators. The bottleneck is not conventional packaging capacity. It is the combined constraint of advanced packaging capacity, yield, materials, equipment, substrates, and customer qualification.
Intel’s EMIB-T and glass-substrate work represent another technology path. Glass substrates matter not because “glass” is a new buzzword, but because next-generation large-area packages require better flatness, dimensional stability, signal integrity, and thermal behavior. As chiplet integration becomes larger and more complex, traditional organic substrates may face limits.
The biggest risk in this area is overgeneralization.
Advanced packaging has a long supply chain and many different business models. Some companies provide packaging services. Some supply substrates. Some provide key materials. Some make equipment. Some control customer qualification and capacity. Some are only indirectly exposed to materials demand.
The real question is not who has exposure to “packaging.” The real question is:
Who is in a critical position inside the AI accelerator package? Whose capability affects yield? Whose capacity affects customer delivery? Whose material determines next-generation electrical or thermal performance?
VIUS’s view is that advanced packaging and substrates are structurally important, but the chain must be analyzed carefully. The key variables are yield, capacity, customer qualification, material barriers, and system integration — not concept labels.
6. New Materials: A Long-Duration Mine, Not a Near-Term Shortcut
Tan mentioned GaN, SiC, InP, glass substrates, and synthetic diamond. This part of the discussion should not be treated as decorative.
From a physics perspective, new materials address the deeper constraints of the post-Moore era.
InP is tied to high-speed optical communication, optoelectronic conversion, and optical interconnect. GaN is tied to high-frequency, high-efficiency power conversion. SiC is tied to high-voltage, high-power systems. Glass substrates are tied to next-generation advanced packaging. Synthetic diamond is tied to extreme thermal conductivity and heat management.
These materials solve different problems, but they point to the same broader trend: as silicon, copper, organic substrates, and traditional thermal paths approach limits, materials become a new performance lever.
This is also the area most likely to be overhyped.
Many GaN and SiC companies still derive most of their revenue from automotive, industrial, adapters, renewable energy, or traditional power electronics rather than AI data centers. InP and optoelectronic materials are more directly connected to optical interconnect, but even there it is necessary to distinguish telecom, datacom, and AI-cluster demand. Synthetic diamond and glass substrates have long-term relevance, but customer validation, manufacturing scale-up, and revenue contribution still take time.
New materials should be treated as long-duration technology reserves, not near-term commercial proof.
A better framework is to divide them into three categories.
The first category is closer to AI data movement: InP, optoelectronic materials, and parts of the silicon-photonics ecosystem. These connect most directly to the interconnect and optical bottleneck.
The second category is closer to power density: GaN and related high-efficiency power-conversion materials. The key question is not the material name, but whether the product enters AI server or rack-level power architecture.
The third category is closer to packaging and thermal management: glass substrates and synthetic diamond. These may matter for next-generation packaging and heat removal, but they require customer roadmaps, production capability, and revenue data before they move from technical logic to business logic.
VIUS’s view is that new materials may become one of the most important long-term research areas in AI semiconductors. But at this stage, the right posture is disciplined observation, not premature commercialization claims.
7. AI-EDA: Chip Complexity Is Becoming Its Own Bottleneck
Tan’s Cadence background matters when he discusses AI-EDA. This is not just a generic claim that “AI can help design chips.”
Chip complexity is rising from multiple directions.
Advanced nodes make design rules more complex. Chiplets and 3D packaging make system integration harder. Power integrity, signal integrity, and thermal constraints require more sophisticated simulation. AI accelerators, robotics chips, and automotive chips need to balance performance, power, reliability, and software ecosystems.
In that environment, design, verification, and simulation become bottlenecks.
In December 2025, Nvidia and Synopsys expanded their partnership, with Nvidia investing $2 billion in Synopsys common stock. The partnership aims to combine Nvidia’s AI and accelerated-computing capabilities with Synopsys engineering-design tools for design, simulation, and verification.
Synopsys also completed its acquisition of Ansys in 2025, combining silicon design, IP, simulation, and analysis more tightly. The company cited a combined total addressable market of $31 billion.
This suggests AI-EDA is not simply an AI feature added to EDA software. It is part of a broader convergence between chip design, system simulation, multiphysics analysis, and AI-native workflows.
The commercial pattern is different from HBM, interconnect, or power delivery. AI-EDA may not show up as a single explosive product line. Its value may instead appear through customer retention, workflow upgrades, expanded simulation demand, design-process redesign, and long-term pricing power.
VIUS’s view is that AI-EDA is a long-duration efficiency tool for a semiconductor industry facing rising complexity. Its value comes from the difficulty of designing advanced chips, not from the AI label itself.
8. From Cloud to Edge: Agentic AI and Physical AI Change Where Compute Happens
Tan also discussed changes in AI workloads and the movement of AI from data centers toward PCs, edge devices, and physical AI.
This needs to be connected to the earlier system bottlenecks.
In the training phase, the main bottlenecks sit inside large cloud clusters. In the inference phase, memory, networking, CPU, storage, and system scheduling become more important. In the agentic AI phase, workloads become more complex. In the physical AI phase, compute moves into robots, industrial equipment, edge cameras, medical devices, retail terminals, and autonomous machines.
Agentic AI is not just single-turn question answering. It requires planning, tool use, database access, file reading and writing, code execution, API calls, retrieval, waiting for feedback, correction, and retry. Much of that workload is control flow, I/O, memory, storage, and system orchestration — not pure matrix multiplication.
That means CPU, memory, I/O, and scheduling may become more important again.
Physical AI introduces another set of constraints. Robots and industrial devices are not merely generating text or images. They are sensing, deciding, and acting in the physical world. They need low latency, low power, sensor fusion, real-time control, local safety, motor control, and industrial-grade reliability.
Intel’s Computex 2026 materials stated that the company has more than 4,000 edge ecosystem partners and more than 100,000 edge deployments across manufacturing, robotics, retail, and other markets. It also described efforts to extend these capabilities into robotics, autonomous machines, and other AI devices.
This suggests the location of AI compute is changing.
But direction is not the same as commercial proof. Edge AI, robotics, and physical AI are long-term trends. They do not imply that every edge chip, sensor, MCU, or industrial-control company will benefit immediately.
The evidence to watch is specific:
Is AI entering customer product roadmaps? Are deployments moving from pilots to scale? Is semiconductor content per device rising? Is local inference creating new chip demand? Are robotics and industrial AI generating stable shipments? Are companies disclosing measurable edge-AI or physical-AI revenue?
VIUS’s view is that this is a demand-structure migration, not a near-term conclusion. It shows that AI semiconductor analysis cannot stop at cloud training clusters. As AI moves into agents, PCs, edge devices, and the physical world, low-power compute, sensors, analog chips, power management, and real-time control become more important. But this layer requires a longer commercial validation cycle.
9. Intel’s Stock Repricing: A Platform Expectation, Not a Single-Product Story
Intel’s stock move after Tan became CEO deserves a short explanation, but not as a stock argument.
On March 12, 2025, Intel announced Tan as CEO. Reuters reported that Intel shares rose 14% the next day. That was an immediate vote of confidence in the leadership change.
Based on historical closing prices used in our data set, Intel rose from $25.92 on March 18, 2025, Tan’s official start date, to $140.94 on June 22, 2026 — roughly a 444% increase. Around June 23, 2026, Intel was still trading near $140, with a market value of roughly $716 billion.
That repricing should not be reduced to one person or one product.
It appears to reflect a broader reset in expectations.
First, management credibility improved. Tan’s Cadence operating record and semiconductor investment background gave investors a reason to believe Intel might become more customer-focused and execution-driven.
Second, the market began to price in organizational repair. Intel had long been criticized for bureaucracy, slow execution, and product-roadmap inconsistency. Tan’s arrival created expectations for a flatter, more engineering-led organization.
Third, advanced packaging and foundry capabilities became more strategically important. AI systems increasingly depend on packaging, manufacturing resilience, and customer trust. If Intel can prove its capabilities in foundry, EMIB, glass substrates, and advanced process technologies, it is no longer viewed only as a CPU company.
Fourth, U.S. semiconductor supply-chain security gained value. AI infrastructure is becoming a strategic asset. Domestic manufacturing, packaging, materials, and advanced-node capability are now evaluated within a broader policy and supply-chain framework.
The higher Intel’s share price rises, the more execution risk matters. The company still needs to prove yield, customer adoption, capital efficiency, external foundry orders, packaging scale-up, and roadmap execution.
In this article, Intel is not a recommendation. It is an industry case study: when the market starts repricing manufacturing, packaging, customer trust, and supply-chain security, semiconductor value is no longer defined only by single-chip performance.
10. Evidence Layers: Tan Is Describing Industry Constraints, Not a Company List
The interview touches many areas. Reducing them to a list of companies would miss the point.
A better approach is to place them into different layers of industry constraint.
Layer 1: Visible Constraint — Memory and HBM
Memory is the strongest current evidence layer. Financial results, supply-demand dynamics, long-term customer commitments, and market repricing have already validated its importance.
Because it is visible, the analysis should move beyond proving that HBM matters. The real work is understanding supply cycles, customer lock-in, competitive response, and whether the memory business is structurally different in the AI era.
Layer 2: Commercially Validating System Interfaces — Interconnect, Optical, and Power Delivery
High-speed interconnect, optical connectivity, and chip-level power delivery used to look like supporting layers. As AI clusters scale, they increasingly affect system performance, energy consumption, and deployment density.
Credo’s revenue growth, Marvell’s acquisition of Celestial AI, and ADI’s acquisition of Empower all indicate that these bottlenecks are starting to be validated through customer demand and capital allocation.
The key question is whether system interfaces are beginning to capture more value in the AI infrastructure stack.
Layer 3: Structurally Important but Complex — Advanced Packaging and Substrates
Advanced packaging is structurally important, but the supply chain is long and business models differ widely.
The analysis should not stop at “packaging exposure.” The key issues are critical capacity, yield, materials, customer qualification, and system-integration capability.
Layer 4: Long-Duration Technology Reserves — New Materials
InP, GaN, SiC, glass substrates, and synthetic diamond all have strong physical logic. Their commercialization stages, however, are very different.
This layer requires discipline. Technical logic becomes business logic only after customer validation, production scale-up, and revenue contribution.
Layer 5: Long-Term Efficiency Infrastructure — AI-EDA
AI-EDA addresses rising chip complexity and design inefficiency. Its value is less about short-term product spikes and more about toolchain position, customer retention, and workflow redesign.
Layer 6: Compute-Location Migration — Agentic AI, Edge, and Physical AI
As AI moves from cloud training into agents, edge devices, and the physical world, semiconductor demand spreads across more device-side and industrial categories.
This layer still requires shipment data, customer adoption, and revenue disclosure.
Conclusion: AI Semiconductor Analysis Should Move From Chip Categories to System Constraints
The value of Tan’s interview is not a set of company names. It is a way to study the semiconductor industry.
Start with the workload. Then identify where the physical system is under pressure. Then ask whether that pressure is validated by customer demand, financial data, M&A, or technology roadmaps. Only then analyze how value may shift across the supply chain.
Using that framework, AI semiconductor analysis is moving from chip categories to system constraints.
Memory has become the most visible bottleneck. Interconnect, optical, and power delivery are moving from supporting layers to system interfaces. Advanced packaging and substrates determine whether multi-chip systems can be manufactured at scale. New materials represent the physical reserve of the post-Moore era. AI-EDA reflects the rising complexity of chip design itself. Agentic AI, edge computing, and physical AI change where compute happens.
VIUS’s conclusion is simple:
Memory is already visible. Interconnect, optical, and power delivery are being commercially validated. Advanced packaging and substrates are structurally important but require careful supply-chain analysis. New materials, AI-EDA, edge, and physical AI are long-duration areas that require evidence over time.
This is not a trading conclusion. It is an industry framework.
The key question is whether a component, material, process, or tool is moving from “useful optimization” to “unavoidable system constraint.”
If it is, it may change how value is distributed across the semiconductor supply chain.
That is the most useful lesson from Tan’s interview.
Source note
Sources for this article are listed below. Company mentions are used as industry examples, technology-path examples, commercial validation cases, or supply-chain participants, not as investment recommendations.
Source Table
| Source | Publisher | Type | Date | Use |
|---|---|---|---|---|
| Re-engineering the Semiconductor Supply Chain with Intel CEO Lip-Bu Tan | No Priors | Other | 2026-06-18 | Primary interview source for Tan's semiconductor supply-chain framework, workload discussion, and bottleneck examples. |
| Intel Appoints Lip-Bu Tan Chief Executive Officer | Intel Newsroom | Company IR | 2025-03-12 | Used for Tan's CEO appointment date, effective date, board role, and Cadence performance summary. |
| Lip-Bu Tan Profile | Walden Catalyst | Other | N/A | Used for Tan's founding of Walden International and long-term semiconductor and AI investment background. |
| Intel shares rise after Lip-Bu Tan CEO appointment | Reuters | Other | 2025-03-13 | Used for the reported 14% stock move after Intel announced Tan as CEO. |
| Micron Technology Inc. Reports Results for the Second Quarter of Fiscal 2026 | Micron Technology | Company IR | 2026-03-25 | Used for memory and AI-era strategic value discussion. |
| SK Hynix overtakes Samsung to become Korea's most valuable company | Reuters | Other | 2026-06-22 | Used for HBM market-share context and memory repricing. |
| Credo Technology Group Holding Ltd Reports Fourth Quarter and Fiscal Year 2026 Financial Results | Credo Technology | Company IR | 2026 | Used for high-speed connectivity revenue validation. |
| Marvell to Acquire Celestial AI | Marvell | Company IR | 2026 | Used for photonic fabric and future commercial roadmap. |
| ADI to Acquire Empower Semiconductor | Analog Devices | Company IR | 2026-05-19 | Used for power-density bottlenecks and server-side power delivery. |
| NVIDIA and Synopsys Announce Strategic Partnership to Revolutionize Engineering and Design | Synopsys | Company IR | 2025-12-01 | Used for AI-EDA, simulation, verification, and workflow integration. |
| Synopsys Completes Acquisition of Ansys | Synopsys | Company IR | 2025-07-17 | Used for design, simulation, and multiphysics integration. |
| Computex 2026: An Intelligent World Built on Silicon | Intel Newsroom | Company IR | 2026 | Used for edge ecosystem partners, deployments, robotics, and physical AI. |
Disclosure
This article is for educational and informational purposes only. It does not constitute investment advice, a recommendation, or a solicitation to buy or sell any security.